1. Field of Use
The present invention relates to a hit predictive cache memory.
2. Prior Art
It is known that cache memories are very fast memories, having small capacity, used in modern data processing systems to store portions of the working memory contents, which portions are from time to time, more frequently used or expected to be used. Cache memories essentially comprise an operand store section and an associative memory or contentable addressable memory (CAM) section for storing the addresses of the operands contained in the cache. If a central processor with its own cache needs an operand, the cache checks if the operand address coincides with one of the addresses stored in the CAM section. If this occurs, this means that the operand is stored in the cache which generates and forwards to the processor a "hit" signal and immediately thereafter sends the requested operand to the processor without any need to perform a read operation in the working memory.
If the requested operand is not stored in the cache, a read operation of the working memory is started by the cache which generally, in addition to transferring the operand read out from working memory to the processor, provides storage of the same operand in one of its memory locations by replacing an operand already contained therein.
Even if, within the cache, the address comparison operation requires only a very short time, in the order of few tenths of a nanosecond, in the modern data processing systems which use faster and faster microprocessors, such time may be excessive and may hamper the microprocessor's performance. That is, the microprocessor has to wait for the hit signal and the subsequent data availability.
The situation is further made worse in the modern systems which use a virtual memory. In such systems, the central processor addresses the operands with a logical address which has to be converted into a memory physical address by a memory address management unit.
In order to avoid system problems and cache complexity, the caches usually operate by comparing physical memory addresses. Between the instant of time at which a central processor generates an operand request, identified by a logical address and the instant at which the cache is ready to provide a hit signal, a time interval elapses which is the sum of the time required to convert the logical address into a physical address plus the comparison time of the cache associative memory. During this time interval, the central processor must generally stay idle and wait, with a consequent reduction in performance even if the central processor generally allows for a certain time delay between the reception of a signal confirming the next occurring availability of the operand (possibly the hit signal) and the effective operand availability.